Most signals of practical interest, such as speech, radar signals, sonar signals and various communication signals such as audio and video signals are analog. Often it is desirable to process these analog signals by digital means. To process an analog signal by digital means, it is necessary to convert the analog signal into digital form.
In analog-to-digital conversion, a smooth and continuous analog signal is converted or quantized into a sequence of numbers having finite precision with discrete values at discrete times. The devices that perform this task are called analog-to-digital (“A/D”) converters (“ADC”). Modern demands for precise, fast processing of such digital signals coupled with the advances in very-large-scale integrated circuit (“VLSI”) technology have resulted in the necessity for cost-effective and highly accurate ADC. There are generally two types of ADC commonly used for high-resolution application, sigma-delta modulator ADC and successive approximation register (“SAR”) ADC. Sigma-delta modulator ADC have certain advantages over SAR ADC, when used for oversampled noise-shaping, including inherent linearity and high tolerance to circuit imperfection.
A sigma-delta ADC is generally comprised of (1) a sigma-delta modulator followed by (2) a digital decimation filter and a (3) low-pass filter. The sigma-delta modulator consists of an analog filter/integrator and an n-bit quantizer enclosed in a feedback loop via an m-bit DAC. The feedback DAC is implemented as an array of finite capacitors configured such that a selected number of these capacitors release their electrical charge into a summing junction that produces an equivalent analog output signal of the m-bit digital input code. The quantizer consists of an array of finite comparators in parallel such that each comparator compares the analog signal at the quantizer input to a reference voltage associated to its own output level. The reference voltage for each comparator in the array is equally spaced by the number of comparators in the array within the A/D positive full-scale and negative full-scale. A common clock latch/triggers the output of the comparators, such that each comparator generates a logic “high” (1) or a logic “low” (0) level, with the parallel output of the comparator representing a digital “thermometer code” equivalent to the analog signal at the quantizer input. This “thermometer code” is digitally processed to generate an n-bit digital word representing the converted analog signal that is the output of the modulator and also fed back into the analog filter loop via the feedback DAC. The error between the modulator analog input signal and the modulator digital output code due to the quantizer is the quantization noise
Together with the analog filter, the feedback loop acts to attenuate the quantizing noise at low frequencies while emphasizing the high frequency noise. Since the signal is sampled at a frequency much higher than the Nyquist rate, i.e., a higher oversampling ratio (“OSR”), high frequency quantization noise can be removed without affecting the signal band of interest by means of a digital low-pass filter operating on the output of the sigma-delta modulator. The digital low-pass filter is implemented together with the decimation filter to convert the data from a high rate, low resolution bit stream to a lower rate, higher resolution digital output through oversampling and decimation. Hence, in operation, the sigma-delta modulator oversamples the signal and shapes the noise out of the band of interest.
In the past, the single-bit (1-bit quantizer with 1-bit feedback DAC) sigma-delta modulator has been the preferred architecture due to its low sensitivity to analog component matching by having a large OSR. This architecture has dominated the market for very high resolution but lower speed ADCs. Recently, there has been a desire for high speed, high resolution sigma-delta ADCs. Disadvantageously, sampling frequency is limited by the capability of the device and silicon process technology. Therefore, in order to achieve a higher output data rate, the ADC must have a lower OSR. Most of the higher speed sigma-delta modulators are taking advantage of the multi-bit and multi-stage noise shaping (“MASH”) schemes in order to compensate for the degradation of the signal-to-noise ratio (“SNR”) due to lower OSR constraints. In the multi-bit scheme, the n-bit and m-bit of the quantizer and feedback DAC respectively is more than 1. In the multi-stage scheme, more than one modulator stage is cascaded.
One of the architectural limitations for SNR and spurious-free-dynamic range (“SFDR”) degradation with increasing input signal swing is due to the maximum signal swing limitation. Any given circuit block has its own maximum input signal swing limitation. An input signal that exceeds this limit is typically clipped or saturated. Signal clipping and saturation causes both harmonic and non-harmonic tones. For example, the maximum signal swing of the switched-capacitor (“SC”) switch is limited by the gate driving voltage, and the maximum signal swing of the integrator is limited by the operational transconductance amplifier (“OTA”) output swing which is usually limited by the power supply. The maximum signal swing limitation in a quantizer is due to the finite quantization level or the 0 dB full-scale range of the A/D converter. As previously noted, the n-bit of the quantizer and the m-bit of the feedback DAC have finite quantization levels